1. Field of the Invention
The present invention relates to a semiconductor memory device or a semiconductor integrated circuit, and in particular to technology for compensating for a data error due to a defect in the semiconductor memory device or the semiconductor integrated circuit having the same incorporated therein.
2. Description of the Related Art
Lowering of a manufacturing yield of a semiconductor integrated circuit due to defects generated in the course of a manufacturing process has been a problem in association with increase in the integration degree of the semiconductor integration circuit.
For example, in an LSI logical circuit, an error may occur in logical value due to such a defect. In order to provide the circuit with defect compensating capability for automatically correcting the error, an additional circuit for defect compensation, e.g., a redundancy circuit must be generally provided on a chip, resulting in enhancing the manufacturing yield.
An example of the technology for enhancing the manufacturing yield by compensating for a defect in an unused area of a semiconductor memory, in particular a read-only memory is described in Japanese Unexamined Patent Publication No. JP-A-1-241100. In this prior art, an additional decoder for detecting access to an unused area or a compensated area is provided in a ROM in addition to the usual decoder. In other words, a control signal is generated by the additional decoder in response to an input of an address for accessing the compensated area. Predetermined fixed data is outputted, in place of data read out from the compensated area, in response to the control signal.
In this manner, it is necessary to provide the additional decoder for compensated area in addition to the usual decoder for accessing a ROM in a prior art. Therefore, increase in the number of elements in the additional decoder, and in turn increase in an area of a chip for the additional decoder has been invited. Further, a maximum number of the compensated areas and the size of each area are fixed based on a structure of the additional decoder so that the flexibility for a compensation system is lack. For example, it is impossible to compensate for a defect in an area which includes consecutive "0" or "1" bits or which has a size smaller than that of the compensated area specified by the additional decoder. If the number of the compensated areas exceeds a maximum number of decoded outputs of the additional decoder, compensation has to be abandoned.
In the above mentioned prior art, the additional decoder having the same scale as that of the usual decoder is required to solve the problems related with the flexibility. This invites a remarkable increase in the number of elements in the additional decoder. A term "the number of compensated areas" means number of compensated areas when a total compensated area is divided into the compensated areas by areas for which compensation is not required, i.e., non-compensated areas and a term "the size of a compensated area" means the dimension of an address space for the compensated area.
The semiconductor memory device which is capable of compensating for a defect by merely adding a less number of elements have been strongly demanded. In order to further enhance the manufacturing yield, it is preferable to provide means for reading out data in a memory area after compensating means is set in a invalid state when a defect exists in the compensating means but no defect exists in a subjective memory area.
Since the compensating means is only overhead for a chip area if a sufficient manufacturing yield has been obtained by learning of the manufacturing process of semiconductor integrated circuits, it is important to verify the validity of the compensating means by checking an error which may occur when the compensating means is not used.